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DSP THEORY, ARCHITECTURE

The DSP56002 is a general purpose Digital Signal Processor composed of an efficient 24-bit digital signal processor core, program and data memories, various peripherals, and support circuitry. The 56000-Family-compatible DSP core is fed by pn-chip program RAM, two independent data RAMs, and two data ROMs with sine, A-law, and (mu)-Law tables. The DSP56002 contains a Serial Communications Interface (SCI), Synchronous Serial Interface (SSI) paralell Host Interface (HI), Timer/Event Counter, Phase-Locked Loop (PLL), and On-chip Emulation (OnCE) port. This combination of features makes the DSP56002 a cost effective, high performance solution for high precision general-purpose digital signal processing.
The 56002 Evaluation Module is a 24 bit system with internal and external memory, 16 bit CS4215 Multimedia Coder/Decoder (CODEC), and a 24 bit 56002 Digital Signal Processor. The DSP56002 has three different busses. The X data bus, the Y data bus, and the Global data bus. Each of these buses is 24 bit long. The processor contains three different types of memory. There is the X memory, Y memory, and the P memory. Each memory location is 24 bits long. Usually, the X and Y memories are used for data storage while the p memory locations are used primarily for program storage. The DSP56002 contains an array of registers, and accumulators. There are the address registers; which are set from r0-r7. These registers are 16 bits wide and are used to store addresses and to point to memory locations. There are the offset registers n0-n7; which also are 16 bits wide. These registers are used primarily for array pointing. For instance, these registers can be used similar to arrays and can offset a memory loaction by the amount specified in the offset register. Next are the modifier registers m0-m7. These registers are used to perform modulo arithmetic. These registers can allow for looping actions in memory locations so in looping algorithms the processor circles around a center location instead of having the program counter traverse down the memory. These registers are 16 bits long. The DSP56002 encompasses an array of acumulators. The listed ones are the A, B, A2, A1, A0, B2, B1, B0. The A and B accumulators are 56 bits long allowing for accurate calculations. The A1, A0, B1, B0 are 24 bits long; while A0, and B0 are only 8 bits long. The A2, A1, A0 accumulators are concatenated to make up the A accumulator, and B2, B1, B0 accumulators make up the B accumulator. The processor also has input registers X, Y, X0, X1, Y0, Y1. The X and Y registers are 48 bits long; while the X0, X1, Y0, Y1 registers are 24 bits long. These registers are part of the longer registers X and Y. The DSP56002 also has a host of other registers such as the Loop Counter (LC), Loop Address (LA), Program Counter (PC), Stack Pointer (SP), Status Register (SR), and the Operating Mode Register (OMR).
The DSP56002EVM board encompasses a CODEC used to process the sampled signals. The function of the CODEC is to convert the analog signal to a digital to be processed and to convert the signal from digital to analog again. This CS4215 CODEC interfaces with port C of the DSP56002EVM to pass the information. The CODEC functions as a frame synchronizer for digital data and puts these streams into frames so they may be transmitted to the processor.

56002 block diagram

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