;********************************************* ; ; INIT.ASM ASSEMBLER PROGRAM ; ; program designed by Mohamed El-Sharkawy,Ph.D ; program written and compiled by Ronald William Bazillion ; ;********************************************* ; init_system macro DEBUG EQU $000200 NO_PREAMP EQU $100000 SAMP_RATE_48 EQU $003000 STEREO EQU $000400 DATA_16 EQU $200000 IMMED_3STATE EQU $800000 XTAL2_SELECT EQU $200000 BITS_64 EQU $000000 CODEC_MASTER EQU $020000 CTRL_WD_12 EQU NO_PREAMP+SAMP_RATE_48+STEREO+DATA_16 ;CLB=0 CTRL_WD_34 EQU IMMED_3STATE+XTAL2_SELECT+BITS_64+CODEC_MASTER CTRL_WD_56 EQU $000000 CTRL_WD_78 EQU $000000 HEADPHONE_EN EQU $800000 LINEOUT_EN EQU $400000 LEFT_ATTN EQU $010000 ;63*LEFT_ATTN = -94.5 dB, 1.5 dB steps RIGHT_ATTN EQU $000100 ;63*RIGHT_ATTN = -94.5 dB, 1.5 dB steps MIC_IN_SELECT EQU $100000 MONITOR_ATTN EQU $001000 ;15*MONITOR_ATTN = mute, 6dB steps OUTPUT_SET EQU HEADPHONE_EN+LINEOUT_EN+(LEFT_ATTN*4) INPUT_SET EQU MIC_IN_SELECT+(15*MONITOR_ATTN)+(RIGHT_ATTN*4) ; DSP56002 ON-CHIP PERIPHERAL ADDRESSES PCD EQU $FFE5 PCDDR EQU $FFE3 PCC EQU $FFE1 CRA EQU $FFEC CRB EQU $FFED SSIDR EQU $FFEF IPR EQU $FFFF BCR EQU $FFFE SSISR EQU $FFEE PLL EQU $FFFD org x:0 RX_BUFF_BASE EQU * RX_data_1_2 ds 1 ;data time slot 1/2 for RX ISR RX_data_3_4 ds 1 ;data time slot 3/4 for RX ISR RX_data_5_6 ds 1 ;data time slot 5/6 for RX ISR RX_data_7_8 ds 1 ;data time slot 7/8 for RX ISR TX_BUFF_BASE EQU * TX_data_1_2 ds 1 ;data time slot 1/2 for TX ISR TX_data_3_4 ds 1 ;data time slot 3/4 for TX ISR TX_data_5_6 ds 1 ;data time slot 5/6 for TX ISR TX_data_7_8 ds 1 ;data time slot 7/8 for TX ISR SSI_FLAG ds 1 ;bit flags used for word index RX_PTR ds 1 ;Pointer for rx buffer TX_PTR ds 1 ;Pointer for tx buffer init_codec equ $40 org p:0 jmp START movep #$14,x:PCDDR ; setup pc2 and pc4 as outputs movep #$0,x:PCD ; D/C~ and RESET~ = 0 == control mode do #500,delay_loop rep #2000 ;100 us delay nop delay_loop nop bset #4,x:PCD ; RESET~ = 1 movep #$3000,x:IPR ; set interrupt priority level andi #$FC,mr ;enable interrupts ; set up buffer with control mode data move #CTRL_WD_12,x0 move x0,x:TX_BUFF_BASE move #CTRL_WD_34,x0 move x0,x:TX_BUFF_BASE+1 move #CTRL_WD_56,x0 move x0,x:TX_BUFF_BASE+2 move #CTRL_WD_78,x0 move x0,x:TX_BUFF_BASE+3 movep #$01E8,x:PCC ;Turn on ssi port ; ; CLB == 0 ; jclr #3,x:SSISR,* ;wait until rx frame bit==1 jset #3,x:SSISR,* ;wait until rx frame bit==0 jclr #3,x:BASE,x0 move x0,x:RX_PTR ;Initialize the rx pointer move x:RX_PTR,r7 ;Load the pointer to the rx buffer. move #TX_BUFF_BASE+1,x0 move x0,x:TX_PTR ;Initialize the tx pointer move x:TX_PTR,r0 ;Load the pointer to the rx buffer. jsr init_codec ;init the output set in the beginning rather than each time move #OUTPUT_SET,y0 ;headphones, line out, mute spkr, no attn move y0,x:TX_BUFF_BASE+2 move #INPUT_SET,y0 ;no input gain, monitor mute move y0,x:TX_BUFF_BASE+3 ;wait for sync to be established and then switch to shorter interrupts do #$100,gothru jclr #2,x:SSISR,* ;wait until tx frame bit==1 jset #2,x:SSISR,* ;wait until tx frame bit==0 nop gothru nop ;set up shorter interrupts to next_rx for receiving and next_tx for trans. move #next_rx,a1 move a1,p:$d move #next_tx,a1 move a1,p:$11 nop endm wait_receive macro ;this macro wait to recieve data jclr #3,x:SSISR,* ;wait until rx frame bit==1 jset #3,x:SSISR,* ;wait until rx frame bit==0 endm wait_send macro jclr #2,x:SSISR,* ;wait until rx frame bit==1 jset #2,x:SSISR,* ;wait until rx frame bit==0 endm get_left macro ;this macro get the left channel to x0 move x:RX_BUFF_BASE,x0 endm put_left macro ;this macro put the left channel from a move a,x:TX_BUFF_BASE endm get_right macro ;this macro get the right channel to x1 move x:RX_BUFF_BASE+1,x1 endm put_right macro ;this macro put the right channel from b move b,x:TX_BUFF_BASE+1 endm wait_word macro jclr #1,r7,* endm